cacheflush on tilegx
flush contents of instruction and/or data cache
sys_cacheflush(unsigned long addr, unsigned long len, unsigned long flags)| number | 245 (0xf5) |
|---|---|
| abi | common |
| entry point | sys_cacheflush |
| since | Linux 3.7 or earlier (3.7 is the first release scanned for tilegx) |
| man page | cacheflush(2) |
| source | elixir.bootlin.com |
Registers
| register | value |
|---|---|
r10 | 245, the syscall number |
r0 | unsigned long addr |
r1 | unsigned long len |
r2 | unsigned long flags |
r0 | the return value |
Then run swint1 to enter the kernel.
The kernel uses r1 to signal an error.
This architecture was removed from the Linux kernel in Linux 4.17. The newest release with a syscall table here is Linux 4.16. The other removed architectures live on the historical architectures page.
Same syscall on other architectures
- mips64 5197
- mipsn32 6197
- mipso32 4147
- arc 244
- blackfin 374, removed in 4.17
- csky 245
- m68k 123
- mn10300 289, removed in 4.17
- nds32 244, removed in 5.18
- nios2 244
- parisc 356
- sh 123
- tilepro 245, removed in 4.17
Get this as JSON: https://api.syscall.sh/v2/syscalls/tilegx/cacheflush?kernel=all